`timescale 1ps/1ps
`define ZYNQ_VIP_0 sim_tb_top.u_design_1_wrapper.design_1_i.zynq_ultra_ps_e_0.inst
`define XILINX_SIMULATOR

module sim_tb_top;
  import arch_package::*;
//////////////////////////////////////////////

reg          com_clk_i;
wire         COM_CLKN0;  
wire         COM_CLKP0;   
wire [3:0]   LED;

///////////////////////////
wire ARESET_N;
reg tb_ACLK;
reg tb_ARESETn;
wire temp_clk;
wire temp_rstn;
reg resp;
reg [31:0] read_data;
reg [127:0] read_data128;
reg [7:0]  irq_status;
reg [31:0] src_data;
reg [31:0] dst_data;

design_1_wrapper
u_design_1_wrapper
(
    .CLK_IN1_D_com_clk_n  (COM_CLKN0           ),
    .CLK_IN1_D_com_clk_p  (COM_CLKP0           ),
    .LED3_0               (LED                 )

);

  //**************************************************************************//
  // Clock Generation
  //**************************************************************************//

  initial begin
    tb_ACLK      = 1'b0;
    com_clk_i    = 1'b0;
  end

  always        tb_ACLK = #(10000/2)  ~tb_ACLK;
  always      com_clk_i = #(40000/2.0) ~com_clk_i;   //25Mhz

  assign COM_CLKP0 =  com_clk_i;
  assign COM_CLKN0 = ~com_clk_i;


    initial begin
        $display ("running the tb");
         tb_ARESETn = 1'b0;
         repeat(200)@(posedge tb_ACLK);
         #5
         tb_ARESETn = 1'b1;
          @(posedge tb_ACLK);
         repeat(200) @(posedge tb_ACLK);

        `ZYNQ_VIP_0.por_srstb_reset(1'b0);
        `ZYNQ_VIP_0.fpga_soft_reset(32'h1);

        #2000000 ;  // This delay depends on your clock frequency. It should be at least 16 clock cycles.
        `ZYNQ_VIP_0.por_srstb_reset(1'b1);
        `ZYNQ_VIP_0.fpga_soft_reset(32'h0);

       // Set debug level info to off. For more info, set to 1.
        `ZYNQ_VIP_0.set_debug_level_info(1);
        `ZYNQ_VIP_0.set_stop_on_error(1);
     
////////////////////////////////////////////////////////////////////////////////////////
        //This drives the LEDs on the GPIO output
        `ZYNQ_VIP_0.write_data(32'hA0000000,4, 32'h00000001, resp);
        `ZYNQ_VIP_0.write_data(32'hA0000000,4, 32'h00000002, resp);
        `ZYNQ_VIP_0.write_data(32'hA0000000,4, 32'h00000004, resp);
        `ZYNQ_VIP_0.write_data(32'hA0000000,4, 32'h00000008, resp);
        $display ("LEDs are toggled, observe the waveform");
////////////////////////////////////////////////////////////////////////////////////////
        //Write into the BRAM through GP0 and read back
        `ZYNQ_VIP_0.write_data(32'hA0010000,4, 32'hDEADBEEF, resp);
        `ZYNQ_VIP_0.read_data(32'hA0010000,4,read_data,resp);
        $display ("%t, running the testbench, data read from BRAM was 32'h%x",$time, read_data);
        if(read_data == 32'hDEADBEEF) begin
           $display ("AXI BRAM Test PASSED");
        end
        else begin
           $display ("AXI BRAM Test FAILED");
        end
        $display ("Simulation completed");
        $stop;
  
    $finish;         
       
  end

    assign temp_clk = tb_ACLK;
    assign temp_rstn = tb_ARESETn;

endmodule