`timescale 1ps/1ps
`define ZYNQ_VIP_0 sim_tb_top.u_design_1_wrapper.design_1_i.zynq_ultra_ps_e_0.inst
`define  XILINX_SIMULATOR

module sim_tb_top;
//  import arch_package::*;
//////////////////////////////////////////////

reg          com_clk_i;
wire         COM_CLKN0;  
wire         COM_CLKP0;   
wire [3:0]   LED;

///////////////////////////
wire ARESET_N;
reg tb_ACLK;
reg tb_ARESETn;
wire temp_clk;
wire temp_rstn;
reg resp;
reg [31:0] read_data;
reg [127:0] read_data128;
reg [7:0]  irq_status;
reg [31:0] src_data;
reg [31:0] dst_data;

int cdma_tb_pass = 1;


design_1_wrapper
u_design_1_wrapper
(
    .CLK_IN1_D_com_clk_n  (COM_CLKN0           ),
    .CLK_IN1_D_com_clk_p  (COM_CLKP0           ),
    .LED3_0               (LED                 )

);

  //**************************************************************************//
  // Clock Generation
  //**************************************************************************//

  initial begin
    tb_ACLK      = 1'b0;
    com_clk_i    = 1'b0;
  end

  always        tb_ACLK = #(10000/2)  ~tb_ACLK;
  always      com_clk_i = #(40000/2.0) ~com_clk_i;   //25Mhz

  assign COM_CLKP0 =  com_clk_i;
  assign COM_CLKN0 = ~com_clk_i;


    initial begin
        $display ("running the tb");
         tb_ARESETn = 1'b0;
         repeat(200)@(posedge tb_ACLK);
         #5
         tb_ARESETn = 1'b1;
          @(posedge tb_ACLK);
         repeat(200) @(posedge tb_ACLK);

        `ZYNQ_VIP_0.por_srstb_reset(1'b0);
        `ZYNQ_VIP_0.fpga_soft_reset(32'h1);

        #2000000 ;  // This delay depends on your clock frequency. It should be at least 16 clock cycles.
        `ZYNQ_VIP_0.por_srstb_reset(1'b1);
        `ZYNQ_VIP_0.fpga_soft_reset(32'h0);

       // Set debug level info to off. For more info, set to 1.
        `ZYNQ_VIP_0.set_debug_level_info(1);
        `ZYNQ_VIP_0.set_stop_on_error(1);
     
////////////////////////////////////////////////////////////////////////////////////////
        //This drives the LEDs on the GPIO output
        `ZYNQ_VIP_0.write_data(32'hA0000000,4, 32'h00000001, resp);
        `ZYNQ_VIP_0.write_data(32'hA0000000,4, 32'h00000002, resp);
        `ZYNQ_VIP_0.write_data(32'hA0000000,4, 32'h00000004, resp);
        `ZYNQ_VIP_0.write_data(32'hA0000000,4, 32'h00000008, resp);
        $display ("LEDs are toggled, observe the waveform");
////////////////////////////////////////////////////////////////////////////////////////
        //Write into the BRAM through GP0 and read back
        `ZYNQ_VIP_0.write_data(32'hA0010000,4, 32'hDEADBEEF, resp);
        `ZYNQ_VIP_0.read_data(32'hA0010000,4,read_data,resp);
        $display ("%t, running the testbench, data read from BRAM was 32'h%x",$time, read_data);
        if(read_data == 32'hDEADBEEF) begin
           $display ("AXI BRAM Test PASSED");
        end
        else begin
           $display ("AXI BRAM Test FAILED");
        end


  ////////////////////////////////////////////////////cdma start//////////////////////////////////////////////////////////////////////////////
    // Set minimum port verbosity. Change to 32'd400 for maximum.
    `ZYNQ_VIP_0.M_AXI_HPM0_FPD.set_verbosity(32'd0);
    `ZYNQ_VIP_0.S_AXI_HP0_FPD.set_verbosity(32'd0);
      
    //Fill the source data area
    `ZYNQ_VIP_0.pre_load_mem(2'b00, 32'h00010000, 4096); // Write Random
    
    //Configure CDMA transfer        
    //The M_AXI_HPM0_FPD interface is configured for 128 bits.
    //Use the write_burst_strb command to control which bytes on the interface to enable for the CDMA register writes.
    //Use the read_burst command to control which bytes on the interface to return for the CDMA register reads.
   
    // Read status
    // read_burst(address, len, size, burst type, lock, cache, prot, data, response)
    `ZYNQ_VIP_0.read_burst(40'h00A0020004, 4'h0, 3'b010, 2'b01, 2'b00, 4'h0, 3'b000, read_data128, resp);
    $display ("%t, running the testbench, CDMA status after reset 32'h%x",$time, read_data128[31:0]);

    // Set the source address
    // write_burst_strb(addr, len, size, burst, lock, cache, prot, data, strb_en, strb, datasize, resp);
    `ZYNQ_VIP_0.write_burst_strb(40'h00A0020018, 4'h0, 3'b010, 2'b01, 2'b00, 4'h0, 3'b000, 128'h00000000000000000000000000010000, 1, 16'h000F, 4, resp);
    // Set the destination address
    `ZYNQ_VIP_0.write_burst_strb(40'h00A0020020, 4'h0, 3'b010, 2'b01, 2'b00, 4'h0, 3'b000, 128'h00000000000000000000000000020000, 1, 16'h000F, 4, resp);
    // Enable Interrupt on Complete
    `ZYNQ_VIP_0.write_burst_strb(40'h00A0020000, 4'h0, 3'b010, 2'b01, 2'b00, 4'h0, 3'b000, 128'h00000000000000000000000000017000, 1, 16'h000F, 4, resp);
    // Read the control register
    `ZYNQ_VIP_0.read_burst(40'h00A0020000, 4'h0, 3'b010, 2'b01, 2'b00, 4'h0, 3'b000, read_data128, resp);
    $display ("%t, running the testbench, CDMA control 32'h%x",$time, read_data128[31:0]);

    // Set bytes to transfer to 0x100 and start transfer.
    `ZYNQ_VIP_0.write_burst_strb(40'h00A0020028, 4'h0, 3'b010, 2'b01, 2'b00, 4'h0, 3'b000, 128'h00000000000000000000000000000100, 1, 16'h000F, 4, resp);
    // Read control register/verify CDMA is running
    `ZYNQ_VIP_0.read_burst(40'h00A0020004, 4'h0, 3'b010, 2'b01, 2'b00, 4'h0, 3'b000, read_data128, resp);
    $display ("%t, running the testbench, CDMA status after transfer started 32'h%x",$time, read_data128[31:0]);
    
    // Wait for interrupt
    `ZYNQ_VIP_0.wait_interrupt(4'h0,irq_status);
    
    if(irq_status & 8'h01) begin
        $display("SUCCESS: CDMA interrupt received");
    end
    else begin
        $display("FAILURE: CDMA interrupt not received");
        cdma_tb_pass = 0;
    end 
  
    // Read the status register
    `ZYNQ_VIP_0.read_burst(40'h00A0020004, 4'h0, 3'b010, 2'b01, 2'b00, 4'h0, 3'b000, read_data128, resp);
    $display ("%t, running the testbench, CDMA status after interrupt 32'h%x",$time, read_data128[31:0]);
    // Check for IRQ error
    if(read_data128[31:0] & 32'h00004000) begin
      $display("FAILURE: Error IRQ received");
      cdma_tb_pass = 0;
    end
   
    if(cdma_tb_pass) 
    $display("Testbench finished");   

    $finish;         
       
  end

    assign temp_clk = tb_ACLK;
    assign temp_rstn = tb_ARESETn;

endmodule